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Journal | [J] 工程技术研究 Volume 4, Issue 8. 2022.
关于提高SoC设计时钟域交叉验证
作者 : GUPTA Vrinda, KASIM Mohammad, JEBIN Mohandas
DOI: 10.12361/2705-0513-04-08-84552
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摘要 / Abstract
摩尔定律一直推动半导体行业大量生产多时钟（大多不相关的）复杂的系统级芯片（SoC）设计。跨越这种不相关或异步时钟域的数据/信号更有可能在稳定之前被采样，从而导致亚稳态等问题。这种时钟域交叉（CDC）信号必须使用同步器有效地在域之间同步，且必须在质量验收前完全验证。如果没有得到适当验证或在设计周期后期才被检测到，这些交叉将导致芯片旋转并增加成本。在基于平面网表的CDC验证检查中，最为典型的困难是超长的运行时间、内存消耗以及数百万次违反调试计数。因此，针对系统级芯片集成电路进行了分层CDC验证方法。这种分层方法在不影响质量的前提下，在内存消耗、签收时间方面改进了SoC的CDC验证。
关键词 / Keywords
SoC亚稳定性；时钟域交叉；同步；重置域交叉；故障
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